| Jul, 2025 | Our paper Re-architecting End-host Networking with CXL: Coherence, Memory, and Offloading has been accepted to MICRO 2025! This work pioneers the use of a CXL Type-2 device to build end-host networking, leveraging its cache coherence, memory expansion, and offloading capabilities. |
| Jun, 2025 | Our work on SSD Latency Prediction has been accepted to IEEE Computer Architecture Letter! In this paper, we develop time series machine learning models to precisely predict SSD access latency, enabling smarter storage system design and optimization. |
| Apr, 2025 | Our work on Memory Deduplication Acceleration has been accepted to USENIX ATC 2025! In this work, we redesign the memory deduplication process to be more efficient by enabling parallel function execution, which are further accelerated by the on-chip accelerator, DSA. This is extensive work from our previous CAL work on DSA. |
| Jan, 2025 | Our work on Data Streaming Accelerator has been accepted to IEEE CAL! In this work, we propose a cooperative memory deduplication scheme between CPU and on-chip accelerator, DSA, to reduce the memory tax. |
| Jul, 2024 | Our work on CXL Type-2 device has been accepted to MICRO 2024! This is the first work on a geniue CXL Type-2 device, showcasing its characterization and potential for heterogeneous computing. |
| Dec, 2023 | Invited talk at OCP Composable Memory System Group call on “Improve System Performance by Offloading Memory-Intensive Kernel Features to CXL Type-2 Device” video. |
| Oct, 2023 | Present the world’s first demonstration of CPU offload using a CXL Type 2 device at Global OCP Summit 2023! Check out the post from Intel. |
| Oct, 2023 | Our work on CXL memory with geniue CXL device accepted to MICRO 2023! |
| Jul, 2023 | Our work on datacenter memory tax reduction accepted to USENIX ATC 2023! |